Complementary metal-oxide-semiconductor (CMOS) technologies have traditionally not been favored for power amplifier applications, because of the inability of field-effect transistors (FETs) to tolerate high voltage levels. Thus, the power provided by a single FET is limited. In recent decades, stacked FETs (coupled in series) have been introduced to overcome the limited CMOS voltage range and applied in power amplifier applications.
In order to get efficient performance, a superior gain, and output power, a conventional stacked FET power amplifier needs at least three individual voltage supplies to meet gate voltage and drain voltage requirements. As shown in FIG. 1, an exemplary stacked FET power amplifier 10 is coupled to individual voltage supplies V1, V2, and V3, and an input signal IN. The stacked FET power amplifier 10 includes a first FET 12 stacked, or coupled in series, with a second FET 14. A gate of the first FET 12 is coupled to V1 and the signal supply IN, a source of the first FET 12 is coupled to ground, and a drain of the first FET 12 is coupled to a source of the second FET 14. A gate of the second FET 14 is coupled to V2, and a drain of the second FET 14 is coupled to V3. An output signal OUT is provided at the drain of the second FET 14 and is an amplified version of the input signal IN.
V1 is set to the voltage required for desired current density, typically near −3V for a Gallium Nitride (GaN) FET. V3 is set to twice the signal FET drain voltage that users desire to bias the FET (e.g. 40V for a 20V process). Ideally, V2 is set to 0.5V3+V1 to ensure neither the first FET 12 nor the second FET 14 experiences compression or breakdown before the other. Deviation of V2 from the ideal voltage will alter voltage at the drain of the first FET 12 (the source of the second FET 14) and create non-ideal and different drain to source voltages for the first and second FETs 12 and 14. Therefore, the first FET 12 or the second FET 14 may experience compression or breakdown before the other. Further, the more individual voltage supplies required by a circuitry, the more area that is needed for the circuitry, which increase cost.
Accordingly, there remains a need to use fewer individual voltage supplies to provide gate/drain biasing to a stacked FET power amplifier.